Vertical Conductive Structure
A new interconnect technology
VeCS is developed as a need for a more intelligent PCB technology that reduces layercount and improves signal integrity without the need go to costly sequential technologies such as Anylayer and MSAP.
VeCS technology is patented and will be licenses to OEM, CEM and substrate fabricators. Contact us when you are interested in a license.
In the X-ray image below we compare PTH and VeCS with mutliple vertical traces (black rectangular shapes in the center of the image). The density of the vertial traces is much higher then can be achieved with PTH. The VeCS-2 technology can stop and a particular layer, with the restriction that always opposite signal in the slot must have the same depth.
In a cross section the VeCS technology looks like is shown in the picture below. The VeCS is embedded between two prepregs and connected by Microvias. The blind slots we call VeCS-2, the through slots we call VeCS-1.
Reducing reflections in transmission lines is one of the areas we focus one with VeCS. Tuning the impedance of the vertical trace using for example a shielded VeCS slot enables the designer to match the vertical and horizontal impedances of the transmission line.
Below we show the shielded VeCS slot in an X-ray image
The TDR graph shows the smoother tuned transition of the VeCS vertical trace compared to the traditional backdrilled PTH. The inductive response showing for the VeCS trace can be shaped further using fieldsolvers to find the correct vertical trace width.
All the work performed on VeCS is focussed on high speed signalling. In order to get the best signal integrity performance the Shielded VeCS.
Next to improving the signal performance we want to reduce the complexity of the circuit board by eliminating the need for sequential lamination and the limits in material types and thickness it requires.
Complex HDI constructions as shown in the following image can be converted using VeCS reducing the complexity to a single lamination.
In the VeCS construction above we show in red how the connections from top to bottom are made connecting a CPU and memory device creating a high dense circuit. This was one of the objectives when developing VeCS was to reduce complexity (read sequential lamination) and to use thicker dielectrics in order to create wider line widths (with keeping impedances Zo at around 50 Ohm or Ziff around 90 - 100Ohm).
VeCS is the acronym for Vertical Conductive Structure and is a new interconnect technology following and adding to the known HDI / Microvia technology without the limitations of HDI. Semiconductor packaging technology is driving the circuit board technology and with the pitches getting smaller and the pin-count more dense HDI is not the solution. Sequential lamination and microvias are a technical solution but not from a cost perspective.